This application claims the priority of Korean Patent Application No. 2004-51, filed on Jan. 2, 2004, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
1. Field of the Invention
The present invention relates to test equipment, and more particularly, to an apparatus for generating a test stimulus signal.
2. Description of the Related Art
After semiconductor devices are fabricated through a manufacturing process, they are examined for defects before being sold. Automatic test equipment (ATE) or IC testers are used to perform such examinations. An ATE is an apparatus which automatically examines the operating efficiency of semiconductor devices, applies test stimulus signals, for example, electric signals, to semiconductor devices under test, and estimates response signals, for example, current values or voltage values of the response signals, output from semiconductor devices under test. An apparatus for generating test stimulus signals is generally used to generate the test stimulus signals applied to the semiconductor devices under test. The test stimulus signals have voltages in a predetermined range. The ATE tests the device under test using voltages of the test stimulus signals.
On the other hand, test stimulus signals having current values that are in a predetermined range are required in order to estimate the operating characteristics of semiconductor devices, especially, semiconductor devices used in communication systems. Accordingly, test stimulus signals having voltage values in a corresponding predetermined range are generated and converted into test stimulus signals having current values in the predetermined range. Conventionally, a resistor is used to convert the test stimulus signals of known voltages into test stimulus signals of known currents.
FIG. 1 is a diagram showing a conventional apparatus for generating test stimulus signal and a device under test. Referring to FIG. 1, an apparatus 10 for generating a test stimulus signal includes a voltage source generation unit 20 and resistances Re1 and Re2. The resistances Re1 and Re2 are connected respectively between output pins 31 and 32, respectively, of the voltage source generation unit 20, and input pins 41 and 42 of a device under test DUT 40. Only two input pins, i.e. 41 and 42 of the DUT 40 are shown in FIG. 1, for simplicity; however, the DUT 40 may have many input pins. Resistances Rn1 and Rn2 in the DUT 40 are equivalent circuits representing parasitic resistances of the input pins 41 and 42, respectively. The voltage source generation unit 20 includes a clock signal generator 21, a source memory 22, a digital to analog D/A converter 23, a low frequency filter 24, an amplification controller 25, a first and second signal combining units 26 and 27, first and second driver amplifiers 28 and 29, and a DC voltage generator 30. The voltage source generation unit 20 generates test stimulus signals TSV1 and TSV2 having predetermined voltages respectively. The test stimulus signals TSV1 and TSV2 are analog signals such as sine waves, and have complementary voltage levels Vpp and Vpn respectively. Since the test stimulus signals TSV1 and TSV2 are analog signals, the voltage levels of Vpp and Vpn are changed periodically.
Referring to FIG. 1, test stimulus signals TSV1 and TSV2 having voltages Vpp, Vpn, are converted into test stimulus signals TSI1 and TSI2 having currents, by the resistances Re1 and Re2. Here, the size of currents Ipp and Ipn flowing in the resistances Re1 and Re2 is determined by the voltages Vpp and Vpn, and bias voltages Vpin1 and Vpin2 in the DUT 40, as indicated in the following equation.
                              Ipp          =                                    (                              Vpp                -                Vpin1                            )                        Re1                          ⁢                                  ⁢                  Ipn          =                                    (                              Vpn                -                Vpin2                            )                        Re2                                              (        1        )            
In the Equation 1, the bias voltages Vpin1 and Vpin2 are determined by internal impedances in the DUT 40, namely, by the resistances Rn1 and Rn2 of the input pins 41 and 42 and the currents Ipp and Ipn. Therefore, when values of the resistances Rn1 and Rn2 are changed, levels of the bias voltages Vpin1 and Vpin2 may be changed. Also, referring to Equation 1, the currents Ipp and Ipn are affected by the bias voltages Vpin1 and Vpin2. Here, since the bias voltage Vpin1 is Ipp×Rn1 and the bias voltage Vpin2 is Ipn×Rn2, the currents Ipp and Ipn are represented by the following equation.
                              Ipp          =                      Vpp                          (                              Re1                +                Rn1                            )                                      ⁢                                  ⁢                  Ipn          =                      Vpn                          (                              Re2                +                Rn2                            )                                                          (        2        )            
The currents Ipp and Ipn, which are applied to the input pins 41 and 42 respectively, should be equal in order to correctly test the operating efficiency of the DUT 40. The bias voltages Vpin1 and Vpin2 should be equivalent to each other in order to let the currents Ipp and Ipn be equivalent to each other. However, it is very difficult to fabricate a DUT having the same bias voltages Vpin1 and Vpin2, because the values of the resistances Rn1 and Rn2 of the input pins 41 and 42 vary in accordance with the conditions of a process for fabricating the DUT.
For example, assuming that the resistances Re1 and Re2 are both 1Ω, and the resistances Rn1 and Rn2 are 3Ω and 1Ω, respectively, the voltages Vpp and Vpn are converted into currents in the range of 8-12 mA. Applying the above values to Equation 2, the resulting current Ipp is in the range of 2-3 mA, while the current Ipn is in the range of 4-6 mA. In this manner, a difference between the currents Ipp and Ipn applied to the input pins 41 and 42, occurs because of a difference in the values of the respective resistances Rn1 and Rn2 of the input pins 41 and 42.
In this case, the currents Ipp and Ipn are adjusted until they are equal by adjusting the levels of the voltages Vpp and Vpn. For example, by adjusting the voltage Vpp to be in the range of 8-12 mV and the voltage Vpn to be in the range of 4-6 mV, the currents Ipp and Ipn then become equivalent in the range of 2-3 mA.
However, referring to FIG. 1, equal DC voltages are input to the input terminals of the first and second driver amplifiers 28 and 29 by the DC voltage generator 30. Therefore, in this configuration, it is impossible or impractical to adjust the voltages Vpp and Vpn to be different from each other.
FIGS. 2A through 2C illustrate waveforms of test stimulus signals TSI1 and TSI2 generated by the apparatus 10 for generating test stimulus signals shown in FIG. 1. FIGS. 2A through 2C show waveforms of the test stimulus signals TSI1 and TSI2 when values of internal impedances in the DUT 40, namely, the values of resistances Rn1 and Rn2, are 50Ω, 100Ω, and 150Ω respectively. Referring to FIGS. 2A through 2C, the currents Ipp and Ipn of the test stimulus signals TSI1 and TSI2 decrease as the values of the internal impedances in the DUT 40 increase.
As described above, since the currents Ipp and Ipn of the test stimulus signals TSI1 and TSI2 generated by the conventional apparatus 10 for generating test stimulus signals vary in accordance with variance in the internal impedance values of the DUT 40, there is a limitation in that the operating efficiency of the DUT 40 cannot be tested accurately.